A fundamental part of the fabrication of semiconductor chips, particularly memory chips, is testing the quality of chips that have been fabricated. As part of quality assurance, tests are often carried out simultaneously on a multiplicity of chips as early as at the wafer level in order to be able to reject faulty chips or to initiate appropriate repair measures as early as possible.
In modern chip production, in conventional test methods, a multiplicity of test modes are loaded into the chips to be tested using a test unit, these test modes are executed, and the test results are output to the test unit. The test modes may be stored in the respective test unit; chips are often also equipped with a corresponding test logic unit in which, inter alia, various test modes may also be stored.
Currently, test modes are often set in the chip to be tested via a serial interface using a bit string in which respective bit sequences are respectively associated with a particular test mode. The bit string is used, for example, to activate/deactivate the test modes, or particular parameters are set in a respective test mode, thus making it possible to change a test mode or, for example, to activate/deactivate particular subfunctions of a test mode. In this case, a complete bit string which comprises the bit sequences for all of the test modes is always transmitted serially even if only a particular test mode needs to be performed or changed.
Due to the increasingly complex structure (associated with progressive miniaturization) of the chips, it is necessary to perform increasingly extensive tests for the requisite quality assurance. However, this results in the serially supplied bit strings generally becoming very long and in it consequently taking a very long time to set or change individual test modes or a plurality of test modes, which may, under certain circumstances, even become time-critical. This problem arises, above all, when one or more test modes are changed over a number of times during a test, which, in practice, may well be the case several thousand times per test. This means, in practice, that, owing to time problems, tests can often be performed only inadequately or cannot be performed at all, with the result that an increased proportion of defective chips which have reached the market can be expected. Furthermore, the very long bit strings which are required for complex chip structures cannot be handled by all test systems, since the bit length of all of the registers in a test system is limited by the hardware. This may lead to considerable overhead time during production.